RTL Modeling with SystemVerilog for Simulation and Synthesis:

Condition - Very Good
The item shows wear from consistent use, but it remains in good condition and functions properly. Item may arrive with damaged packaging or be repackaged. It may be marked, have identifying markings on it, or have minor cosmetic damage. It may also be missing some parts/accessories or bundled items.

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
Country USA
Manufacturer Sutherland HDL, Inc.
Binding Kindle Edition
ReleaseDate 2017-06-15
Format Kindle eBook

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design